DRAMs are an acronym for dynamic random-access read-write memories. In such memories, data can only temporarily be stored, requiring that the memory be continually refreshed or the data rewritten into the memory. In a typical DRAM memory capacitors are charged above a predetermined level for storing data, but such storage is temporary because of parasitic leakage currents in the storage cell. However, the small size of DRAM memory cells has resulted in their widespread usage in data processing apparatus. Major research efforts are ongoing in the present field of technology to provide more economic and improved methods for producing DRAMs, and for reducing or eliminating the leakage currents associated with such devices.
As shown in FIG. 1, a typical DRAM cell includes a MOS transistor 3 connected with its channel between a bit line 4 and a node 6, the latter being connected to one end of a capacitor 8, as shown. The other end of capacitor 8 is connected via a node 10 to a source of DC voltage V. The transfer gate 11 of transfer transistor 3 is connected to a word line 12, as shown. Write operations are performed by typically raising the voltage on the word line 12 to a high level for fully turning on transistor 3. Shortly thereafter the bit line 4 is driven high or low for either charging capacitor 8 to a high level voltage, or to a low level reference voltage, such as ground, for example. After performing this write operation, the word line 12 is then returned to a low level of voltage, for turning off transistor 3, causing its channel to go from a low level impedance to a very high level of impedance for isolating node 6, and as a result capacitor 8, from the bit line 4. If capacitor 8 was charged during the write operation, the charge will slowly leak away due to leakage currents inherent in DRAMs. In operating DRAMs, it is therefore necessary to refresh the device or rewrite the data into the device before the voltage on capacitor 8 discharges to a level that is indeterminate for indicating whether the capacitor is storing a digital "1" or "0". Accordingly, DRAM devices can be made more efficient if the leakage currents are reduced, whereby the device will not have to be as refreshed as often.
The typical device configuration for the corresponding equivalent circuit schematic diagram of FIG. 1 for a DRAM, is shown in FIG. 2. This latter figure is illustrative of a DRAM fabricated using known trench technology, wherein a capacitor cell 14 is fabricated by etching a deep trench 16 into an associated semiconductor substrate 18. A thin dielectric or node dielectric 19 is deposited on the inside wall of the trench 16, followed by filling the trench 16 with a highly n+ doped polysilicon or polyfill 20, in this example. The polysilicon 20 and the semiconductor substrate 18 are equivalent to the two electrodes of the DRAM's capacitor 8. Two n+ doped wells 22 and 24 are formed in the p-doped substrate 18, for providing the drain and source electrodes for the transistor 3. Dislocations generated around the trench cell 16 during processing for producing the DRAM cell are the primary contributors to leakage currents that tend to discharge the capacitor 8.
A buried plate 26 is provided in a n+ doped region within substrate 18, as shown. The highly doped buried plate region 26 surrounds a substantial portion of the trench 16, in order to enhance the use of the semiconductor substrate 18 as a viable capacitor-electrode. A small parasitic transistor 28 is shown schematically as being located between the buried plate 26 and a drain (or source) 22 of the transfer MOS transistor 3. Note that the node dielectric 19 acts as a gate oxide for the parasitic transistor 28. The parasitic transistor 28 tends to discharge the capacitor 8 during storage time periods, but in the extreme this parasitic capacitor 28 may also short the trench capacitor 8 formed in the substrate 18.
In using known technology, dislocations around deep trenches filled with oxide and polysilicon in a monocrystalline silicon substrate are difficult to control. It is believed that stress generated by the different thermal expansion coefficients of the trench 16 while being filled with polysilicon 20, relative to the semiconductor substrate 18, contributes to the control problems. It is preferred that trenches such as trench 16 be filled with highly doped polysilicon in a manner substantially avoiding any voids, in order to minimize stress. Care must also be taken in subsequent processing to substantially avoid oxidation of the sidewalls of the trench 16. These problems can presently only be minimized using known technology by employing an extraordinary amount of engineering time and regulating the associated process flow.
Also, in using presently known DRAM-trench technology, the parasitic transistor 28 cannot be completely eliminated. However, the parasitic transistor 28 can be substantially reduced through use of a collar oxide 30, as shown in FIG. 3, in place of an upper portion of a thin node dielectric 19. The thick collar oxide 30 serves to increase the threshold voltage of the parasitic transistor 28 to values higher than those typically encountered during normal operation of a DRAM cell, thereby reducing the negative effects of the parasitic transistor 28. Note also the use of a strap 32 for connecting drain (or source) electrode 22 to the polyfill 20 of trench 16 representing one plate of capacitor 8.